Therefore the counter will count up.Īsynchronous Up-Down Counter Circuit Diagram Likewise, the non-inverted o/p of Flip Flop1 will be gated through the other NAND gate into the clock i/p of flip-flop2. When the UP i/p is at 1 & the DOWN i/p is at 0, the NAND gate between FF0 & FF1 will gate the non-inverted o/p (Q) of flip flop (FF0) into the clock i/p of flip flop (FF1). The below circuit is a three bit up & down counter, that counts UP or DOWN based on the control signal status. In particular applications, a counter must be capable to count both up & down. Sequence of the Decade Counter Asynchronous Up-Down Counters The series of the decade counter table is given below. At the same time one of the other states from 0-9 have both Q1&Q3 will be high. Notice that only Q1&Q3 both are used to decode the count of 10, that is called partial decoding. When the counter counts to ten, then all the FFs will be cleared. Asynchronous Decade Counter Circuit Diagram A counter with 10-states in its series is called a decade counter.The implemented decade counter circuit is given below. A common modulus for counters with shortened sequence is 10. of states in their series.These are called shortened sequences which are accomplished by driving the counter to recycle before going through all of its states. But, counters with states less than 2n is also possible.
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